Navigating the Rapids and Eddies of Your Design Flow
Co-sponsored by Women In Engineering
Why do bugs cost more the later they are found? Why are projects over
budget? How can we get a handle on the design process?
System on Chip development requires a complex, staged design
flow. It is usually clear there is room for improvement, but where exactly?
This presentation describes an intuitive model of staged development
which can be used to measure, analyze, and improve the design flow.
Cost for luncheon: $18
Registration necessary. Seating is limited.
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Location: Mirabelle Restaurant http://www.mirabellerestaurant.com/ 8127 Mesa Drive Austin, Texas United States |
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Date: 11-November-2009 Time: 11:30AM to 01:00PM (1.50 hours) All times are: America/Chicago |
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iCalendar (2.0-ical): Download or import iCal file into Calendar program (e.g. Outlook)
No Admission Charge.
Speaker:
Ken albin
Topic: Navigating the Rapids and Eddies of Your Design Flow
Ken Albin is a Senior Member of Technical Staff at Advanced Micro Devices in Austin, Texas. He is currently working in the AMD Verification Center of Expertise focusing on verification methodology and metrics. He earned BSEE and MSEE degrees at Kansas State University in 1981 and 1984 respectively. Prior to joining AMD, Ken worked in the Processor Technology department at Rockwell-Collins in Cedar Rapids, Iowa; formal verification research firm Computational Logic Inc; and on advanced verification tools and methodology at Motorola/Freescale Semiconductor.
Topic: Navigating the Rapids and Eddies of Your Design Flow
Ken Albin is a Senior Member of Technical Staff at Advanced Micro Devices in Austin, Texas. He is currently working in the AMD Verification Center of Expertise focusing on verification methodology and metrics. He earned BSEE and MSEE degrees at Kansas State University in 1981 and 1984 respectively. Prior to joining AMD, Ken worked in the Processor Technology department at Rockwell-Collins in Cedar Rapids, Iowa; formal verification research firm Computational Logic Inc; and on advanced verification tools and methodology at Motorola/Freescale Semiconductor.
Meeting Agenda:
11:30 Networking and lunch
12:00 Presentation
1:00PM Adjourn
11:30 Networking and lunch
12:00 Presentation
1:00PM Adjourn

