IEEE Young Professionals Leadership Conference 2014 -- Career Paths and Personal Journeys of Select Intel and IEEE Leaders

Event Description

IEEE Phoenix Young Professionals in collaboration with Women in Engineering and IEEE/IEEE-Eta Kappa Nu ASU groups is organizing our first leadership conference as part of IEEE Young Professionals Strategic Alliance initiative.

Please join us to learn about career paths and personal journeys of select Intel and IEEE leaders that can offer lessons on achieving excellence in leadership. Further, the conference will provide networking opportunities. An Intel Recruiter may also be present at the event to collect resumes.

Notes (for IEEE / non-Intel attendees):

• Attendees will have the opportunity to purchase lunch from Intel Chandler Cafe during lunch break.
• Seating is limited to 100 attendees. Admittance to the event is first come first served.
• Government issued ID will be required to check-in on the day of the event.

Agenda

Speaker Biographies

David Baker, Director - Personal Form Factor Engineering, Software and Services Group, Intel Corporation

David currently manages a 30 person application engineering team. We work closely with mobile software companies, mostly in North America, to port and optimize their apps on Intel-based phones and tablets. We also run an innovation pipeline that quickly develops proof-of-concept apps to explore new user experiences.

With 21 years of Intel experience in embedded processors, application engineering, operations, marketing, Mergers and Acquisitions, healthcare and enterprise strategic partner engagements, David has managed a range of development tool, simulation and product engineering teams.

David holds a MSEE from Washington University and a BSEE from University of Michigan, and is patiently waiting for Michigan to return to collegiate football.

Michael Bair, Principal Engineer, Intel Corporation; BSEE University of Michigan

Michael is primarily centered in the world of HW Validation, but spends the majority of his time attempting to optimize Validation for the whole: SW, FW, Platform, and Devices. Michael began his career on the original Intel Pentium 4 design and continued on through other CPUs such as the Nehalem and Haswell processors, and currently works in the world of devices. Michael wrote much of the HW Validation philosophy for Intel, driving training and standards for much of the company. Beyond the technical day-job, Michael also spends considerable time building relationships between teams and teaching leadership, influencing, and career path classes.

Hang Nguyen, Sr. Principal Engineer and Lead CPU Architect, Intel Corporation

Hang Nguyen holds a BSEE degree from the University of Tennessee in Knoxville and an MSEE degree from the Georgia Institute of Technology. She worked at General Electric Semiconductor before joining Intel in 1987. She has contributed to multiple Intel CPU architectures and micro-architectures spanning from XScaleTM to Itanium Processor Family to Intel Architecture. She was the lead architect for Intel’s first Embedded Xeon-class processor with PCI Express and Storage acceleration integration. Hang became a Senior Principal Engineer in 2010 and is currently the lead CPU and IA products architect for the Communications and Storage Infrastructure Group. Her areas of research interest include resilient computing and real time architectures. Hang holds more than 20 patents with many more pending.

Michael R. Andrews - IEEE R6 Director; Managing Partner, Andrews & Associates; President, Sound & Optics Systems

Please find here.

Prital Shah - Sr Software Engineer, Mobile User Experience, PFF, SSG, Intel

Prital is the Chief Innovation Evangelist and drives creation of Innovative Proof of Concept. She uses the Design Thinking process for ideation to solve real user pain points, creates the Innovative experiences which don’t exist in market today and inspire and work with ISV’s to use these and create innovative products on Intel platform.

She received her BS in Computer Science in India and MS in Computer Science and Engg. from Penn State University in 2001. She joined Intel as a RCG. She has been in sever roles from test engineer, developer, program manager, technical lead and architect in TMG. She moved to SSG in 2008 and have worked with external ISV like Adobe to have their apps work best on Intel platforms.

Shamala Chickamenahalli - Chair, IEEE Phoenix Women in Engineering; Staff Research Engineer, Intel Corporation

Please find here.

Shafiul "Jacky" Islam - Chair, IEEE Phoenix Young Professionals; Software Engineer, Intel Corporation

Please find here.

Organizing Committee

Co-Chairs

• Shafiul "Jacky" Islam (shafiul.islam@intel.com)
• Shamala Chickamenahalli (shamala.chickamenahalli@intel.com)
• Lesley Polka (lesley.a.polka@intel.com)

Members

• Jennifer Taggart (jennifer.taggart@asu.edu)
• Ashley Kelly (Ashley.Kelly@aps.com)
• Nick Spirakus (nmspirak@asu.edu)
• George Chen (gchen32@asu.edu)
• Divya Kalimuthu (divya.kalimuthu@intel.com)
• Joseph Caglio (joseph.m.caglio@intel.com)
• Ahmet Durgun (ahmet.c.durgun@intel.com)

Mentors

• Michael Bair
• Mike Andrews
• Beverly Deason

Intel Campus Relations Manager for ASU

• Lori Torres (loretta.r.torres@intel.com)

• Date: 16 Dec 2014
• Time: 09:45 AM to 04:00 PM
• All times are America/Phoenix
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• 5000 West Chandler Blvd
• Major intersection: Rural and Galveston
• Chandler, Arizona
• United States 85226
• Building: CH7
• Room Number: 111

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• Shafiul "Jacky" Islam (shafiul.islam@intel.com)

  Shamala Chickamenahalli (shamala.chickamenahalli@intel.com)

  Lesley Polka (lesley.a.polka@intel.com)

• Co-sponsored by Intel Corporation

• Starts 22 November 2014 02:15 PM
• Ends 16 December 2014 09:00 AM
• All times are America/Phoenix
• No Admission Charge

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