The Center for Signal Integrity at Penn State Harrisburg will host the Fourteen  Central Pennsylvania Symposium on Signal Integrity, Friday, April 16, 2021 from 8:30 a.m. to 4:30 p.m. online. Zoom links will be sent to participants who register on this website, please provide your email at registration time. Signal integrity involves the quality of electrical signals passing through connectors used in electronic devices like computers or cellular phones. This event is the re-start of our annual symposium since last year's was cancelled due to COVID. The symposium is co-sponsored by IEEE Susquehanna Section and the Center for Signal  Integrity, Penn State Harrisburg.

  Date and Time




  • Date: 16 Apr 2021
  • Time: 08:30 AM to 04:30 PM
  • All times are US/Eastern
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https://harrisburg.psu.edu/center-for-signal-integrity.  Zoom links will be provided to those who register.

  • 777 West Harrisburg Pike
  • Middletown, Pennsylvania
  • United States 17057
  • Click here for Map
  • Dr. Aldo Morales, awm2@psu.edu

    Dr. Sedig Agili, ssa10@psu.edu

    Mrs. Deb Miller, dmm79@psu.edu

    Mrs. Kelly Batche, klb68@psu.edu

  • Co-sponsored by Penn State Harrisburg
  • Starts 26 February 2021 07:30 AM
  • Ends 16 April 2021 08:30 AM
  • All times are US/Eastern
  • Admission fee ?


Dr. Tracey Vincent


Effects of PCB Technological Features on Channel Operating Margin (COM)

Mr. Bill Hargin


How to Avoid Getting Totally Skewed




Detailed abstracts and bios can be found at



April 16, 2021 ZOOM


8:30 to 9:30

Welcoming Remarks

Dr. John Mason, Chancellor, Penn State Harrisburg


Speaker 1

Title: Effects of PCB Technological Features on Channel Operating Margin

Mr.  Longfei Bai. CST, Dassault Systèmes, Dr. Tracey Vincent, Heavyside Corp

Abstract: The coupling (weak vs. strong) in edge-coupled differential transmission lines on a printed circuit board (PCB) affects frequency behavior of mixed-mode S-parameters. Slightly imbalanced stripline differential pairs are considered with various technological features modeled, including the presence of an epoxy-resin " pocket " (EP) between the stripline traces. The study is carried out using full-wave simulation and corroborated with measurement. After the differential pairs are examined the model is used for the calculation of the Channel Operating Margin (COM) which is an efficient method to evaluate high speed interconnects. Effects of PCB technologies on COM are studied with a 1000GBASE-KP4 link. 

Dr. Tracey Vincent is a Senior Support Engineer at Heavyside Corporation.

Mr. Longfei Bai has been an application engineer in SIMULIA CST, Dassault Systèmes since 2015.

9:40 to 11:00

Keysight Workshop

Title: Power Integrity Target Impedance Says it All, Power Delivery is AC not DC!

Heidi Barnes


Power Integrity is all about the insatiable demand for information processing that is demanding complex custom point of load power rails to deliver efficient low noise power to dynamic switching loads.  The analog world loves to argue filter design with inductive beads and snubbers, while the new world of Power Integrity has introduced the concept of Target Impedance. This workshop will immerse you in the world of using and understanding impedance to deliver resonant free power to the load.  Along the way you will learn why flat impedance is the best design, how to measure impedance, and what is wrong with capacitor vendor data.


Heidi Barnes is a Senior Application Engineer and Power Integrity Product Owner for High Speed Digital applications at Keysight Technologies.

11:10 to 12:10

Speaker 2

Title:  How to Avoid Getting Totally Skewed

Bill Hargin
Z-Zero Corporation


In this presentation, we will cover the causes of glass weave skew (GWS) as well as multiple possible solutions, with an eye toward cost and future-proofing your designs, preventing design and manufacturing teams from getting blind-sided by this issue.

Bio: Mr. Bill Hargin served as product manager for Mentor Graphics’ HyperLynx SI software. He now works on Z-Zero Corporation.

12:10 to 12:30

Lunch Break

12:50 to 1:50


Lunch Speaker

Title: Edge inference platform design for IoT/5G generation hardware with machine learning and artificial intelligence

Mr. Chris Cheng, Distinguished Technologist in Primary Storage Division Hewlett-Packard Enterprise.


With the upcoming IoT/5G generation of hardware platforms, it is expected that most of the inference of data will be done at the edge or on prem at the customer sites instead of the current cloud based approach. With these high performance inference engines close to the hardware platforms, we can take advantage of their intelligence for our hardware reliability, system performance tuning and intelligent resource caching. Our presentation will be divided into three class of examples in edge inference applications.

Big data, small learning example

Big data, medium learning example

Big data, deep learning example

Bio: Chris Cheng is responsible for managing hardware machine learning development and high speed design within HP Storage Division.

2:00 to 3:00

Speaker 3

Title: Machine Learning Applications of SI/PI

Dr. Zhiping Yang and Dr. Tianjian Lu, Google corporation

Abstract: In this presentation, we discuss four case studies of machine learning, two are related to power integrity including (1) the application of genetic algorithms and neural networks (NNs) in optimizing decoupling capacitor placement and (2) the impedance prediction of power distribution networks with NNs; and the other two are related to signal integrity including (1) the prediction of eye-diagram metrics through solving a regression problem with support vector machines and NNs and (2) the  predictions on the circuit-level transient behaviors with recurrent NNs.

Tianjian Lu (S’13–M’17) Since 2016, he has been a Hardware Engineer with Google, Mountain View, CA. His research interests include signal and power integrity, and machine learning.

Zhiping Yang (S’97–M’00–SM’04) He is currently a Senior Hardware Manager with Google Consumer Hardware Group, Mountain View, CA, USA.


 3:05 to 4:20


Workshop 2

Eric Oseassen, Rohde & Schwarz USA, Inc. and Jason Ellison, Amphenol LLC

Title:  De-embedding

Abstract: We’ll discuss measurements for characterizing high speed PCBs, cables and connectors exploring how to use these measurements for quantifying the Signal Integrity of these interconnects. We’ll take a close look at test fixture de-embedding, typical use case, and the IEEE 370 standard, as well as the open-source de-embedding method (available on IEEE 370’s GITLAB site). We’ll introduce the integration of this method as Eazy Deembedding (EZD) in Rohde & Schwarz network analyzers, and discuss the difference between normal 2x-thru and impedance corrected 2x-thru de-embedding and the advantages over TRL.


Eric Oseassen

Eric is an application engineer Rohde & Schwarz America. He holds a BSc from the City College of New York and an MSc from NYU Polytechnic.

Jason Ellison

Jason currently works as a Signal Integrity Engineer, developing high-speed interconnects, lab automation technology, and calibration technology at Amphenol. He founded Arcane Technologies LLC.