Integrated Signal and Power Integrity for High-Speed Channel Design

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IEEE Southeastern Michigan: Chapter VIII (EMC)

Southeastern Michigan IEEE EMC Chapter technical meeting.



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  Date and Time

  Location

  Contact

  Registration


  • 19000 Hubbard Drive
  • Dearborn, Michigan
  • United States 48126
  • Building: University of Michigan - Dearborn -Fairlane Center North
  • Room Number: See Monitor in Lobby
  • Click here for Map

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  Speakers

IEEE EMC Distinguished Lecturer Dale Becker

IEEE EMC Distinguished Lecturer Dale Becker

Topic:

Integrated Signal and Power Integrity for High-Speed Channel Design

The high frequency of off-chip signal channels is creating the necessity for increasingly integrated signal and power analysis in the design of the high-speed channels in packages and printed circuit boards. This trend will continue because of the growth of big data and analytics and the demand that puts on computer architectures. The electrical engineer needs the skills to design the hardware in a cost-effective way. This presentation will cover the modeling of the signal distribution at the chip, package and PCB level and the use of transmit and receive models and challenges in modeling, analyzing and quantifying the impact of the power distribution on the eye parameters and jitter. The outputs of the analysis include physical design parameters such as decoupling capacitor requirements, signal shielding requirements and trace placement as well as electrical parameters such as voltage tolerance and jitter output that need to be determined for the full channel design.

Biography: Dale Becker received the B.E.E degree from the University of Minnesota, M.S.E.E. from Syracuse University and the Ph.D. from the University of Illinois at Urbana Champaign. He is a Distinguished Engineer in IBM Systems and Technology Group and a member of the IBM Academy of Technology. He is the System Electrical Architect for the IBM POWER and System Z Enterprise Systems. His responsibilities include designing the high-speed channels to enable the computer system performance and the power distribution networks for reliable operation of the integrated circuits that make up the processor subsystem.
Dr. Becker is the Chair of the IEEE EPEPS 2014 Conference and co-chair of the IEEE EMCS embedded conference on SIPI TPC. He has 25 patents on electrical design of computer systems and has presented 75 papers in refereed journals and international conferences covering many aspects of electrical computer system design including power distribution analysis and design and modeling of signal and power distribution networks. He is a senior member of IEEE, a iNEMI Technical Committee member and a member of IMAPS and SWE.

Email:

Address:New York, United States





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