IEEE CTS CAS/SSC March Meeting:The Annual Review of the ISSCC Conference: Digital, Processor and Memory

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The Annual Review of the ISSCC Conference: Digital, Processor and Memory



  Date and Time

  Location

  Contact

  Registration



  • 201 East 24th St
  • Austin, Texas
  • United States 78712
  • Building: Building: ACES (or POB) 2.402 and 2.402 B (for refreshments)
  • Click here for Map

Staticmap?size=250x200&sensor=false&zoom=14&markers=30.2867487%2c 97
  • See link to map above. Occasionally you might find street level parking for free -- but watch out for the parking signs and restrictions. Another place to park is SJG, the San Jacinto Garage -- after 6PM, it is $7 to park all night.

  • Starts 01 February 2016 09:25 PM
  • Ends 08 March 2016 02:00 PM
  • All times are US/Central
  • No Admission Charge
  • Register


  Speakers

Betty Prince

Topic:

The Annual Review of the ISSCC Conference: Digital, Processor and Memory

memory summary

Biography:

Dr. Betty Prince is CEO of Memory Strategies International and has 35 years engineering experience in the semiconductor industry. She is author of several books in the semiconductor memory area. She is a Senior Life Member of the IEEE and an IEEE SSCS Distinguished Lecturer. She has been active in standardization and has been on the Technical Advisory Board of several memory companies. She has a Ph.D. from the University of Texas with doctoral dissertation on fractal modeling.

Address:Texas, United States

Eric Fluhr

Topic:

The Annual Review of the ISSCC Conference: Digital, Processor and Memory

digital summary

Biography:

Eric Fluhr joined IBM in 1996 after graduating with BSCS and MSEE degrees from the Georgia Institute of Technology. Eric began his career in circuit design and verification on the POWER3 and POWER4 series. He switched to microarchitecture and logic design for POWER5, with a focus on data prefetch. For POWER6®, Eric was the Load/Store-Unit circuit lead and, later, chip characterization lead. As the POWER6+™processor head engineer he was responsible for all chip design changes and hardware characterization for frequency and yield, as well as the technical interface to technology development, system product bring-up, and manufacturing teams. He was subsequently the POWER8® core circuit lead, also responsible for implementing statistical timing for IBM’s 32nm and 22nm server processors, and currently leads chip-level circuit-design on POWER9®. Eric is currently a chip circuit lead for IBM’s POWER®design team.

Betty Prince

Topic:

The Annual Review of the ISSCC Conference: Digital, Processor and Memory

Biography:

Address:Texas, United States

Eric Fluhr

Topic:

The Annual Review of the ISSCC Conference: Digital, Processor and Memory

Biography:





Agenda

6:30 to 7:00 pm -- Networking and refreshments (pizza and water) in POB 2.402B

7:00 to 8:30 pm – Seminar in POB 2.402